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1/13 august 2001 n high speed: f max = 79 mhz (typ.) at v cc =6v n low power dissipation: i cc =4 m a(max.) at t a =25 c n high noise immunity: v nih =v nil =28%v cc (min.) n symmetrical output impedance: |i oh |=i ol = 6ma (min) n balanced propagation delays: t plh @ t phl n wide operating voltage range: v cc (opr) = 2v to 6v n pin and function compatible with 74 series 646 description the 74hc646 is an advanced high-speed cmos octal bus transceiver and register (3-state) fabricated with silicon gate c 2 mos technology. this device consists of bus transceiver circuits with 3 state, d-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. data on the a or b bus will be clocked into register on the low to high transition of the appropriate clock pin (clock ab or clock ba). enable (g) and direction (dir) pins are provided to control the transceiver functions. in the transceiver mode, data present at the high-impedance port may be stored in either register or in both. the select controls (select ab select ba) can multiplex stored and real time (transparent mode) data. the direction control determines which bus will receive data when enable g is active (low). in the isolation mode (enable g high), oao data may be stored in one register and/or obo data may be stored in the other register. when an output function is disabled, the input function is still enabled and may be used to store and transmit data. only one of the two buses, a or b, may be driven at a time. all inputs are equipped with protection circuits against static discharge and transient excess voltage. m74hc646 octal bus transceiver/register with 3 state outputs pin connection and iec logic symbols order codes package tube t & r dip m74hc646b1r sop m74hc646m1r M74HC646RM13TR tssop m74hc646ttr tssop dip sop
m74hc646 2/13 input and output equivalent circuit pin description truth table x : don't care z : high impedance qn : the data stored to the internal flip-f lops by most recent low to high transition of the clock inputs * : the data at the a and b bus will be stored to the internal flip-flops on every low to high transition of the clock inputs. pin no symbol name and function 1 clock ab (cab) a to b clock input (low to high, edge-triggered) 2 select ab (sab) select a to b source input 3 dir direction control input 4, 5, 6, 7, 8, 9, 10, 11 a1 to a8 a data inputs/outputs 20, 19, 18, 17, 16, 15, 14, 13 b1 to b8 b data inputs/outputs 21 g output enable input (active low) 22 select ba (sba) select b to a source input 23 clock ba (cba) b to a clock input (low to high, edge triggered) 12 gnd ground (0v) 24 v cc positive supply voltage g dir cab cba sab sba a b function hx inputs inputs both the a bus and the b bus are inputs x x x x z z the output functions of the a and b bus are disabled x x inputs inputs both the a and b bus are used for inputs to the internal flip-flops. data at the bus will be stored on low to high transition of the clock inputs. lh inputs outputs the a bus are inputs and the b bus are outputs xx*l x ll the data at the a bus are displayed at the b bus hh x* l x l l the data at the a bus are displayed at the b bus. the data of the a bus are stored to internal flip-flop on low to high transition of the clock pulse hh xx*h x x qn the data stored to the internal flip-flop are displayed at the b bus. x* h x l l the data at the a bus are stored to the internal flip-flop on low to high transition of the clock pulse. the states of the internal flip-flops output directly to the b bus. hh ll outputs inputs the b bus are inputs and the a bus are outputs. x* x x l ll the data at the b bus are displayed at the a bus hh x* x l l l the data at the b bus are displayed at the a bus. the data of the b bus are stored to the internal flip-flop on low to high transition of the clock pulse. hh x*xxh qn x the data stored to the internal flip-flops are displayed at the a bus x* x h l l the data at the b bus are stored to the internal flip-flop on low to high transition of the clock pulse. the states of the internal flip-flops output directly to the a bus. hh
m74hc646 3/13 logic diagram timing chart
m74hc646 4/13 absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied (*) 500mw at 65 c; derate to 300mw by 10mw/ c from 65 cto85 c recommended operating conditions symbol parameter value unit v cc supply voltage -0.5 to +7 v v i dc input voltage -0.5 to v cc + 0.5 v v o dc output voltage -0.5 to v cc + 0.5 v i ik dc input diode current 20 ma i ok dc output diode current 20 ma i o dc output current 35 ma i cc or i gnd dc v cc or ground current 70 ma p d power dissipation 500(*) mw t stg storage temperature -65 to +150 c t l lead temperature (10 sec) 300 c symbol parameter value unit v cc supply voltage 2to6 v v i input voltage 0 to v cc v v o output voltage 0 to v cc v t op operating temperature -55 to 125 c t r ,t f input rise and fall time v cc = 2.0v 0 to 1000 ns v cc = 4.5v 0 to 500 ns v cc = 6.0v 0 to 400 ns
m74hc646 5/13 dc specifications symbol parameter test condition value unit v cc (v) t a =25 c -40 to 85 c -55 to 125 c min. typ. max. min. max. min. max. v ih high level input voltage 2.0 1.5 1.5 1.5 v 4.5 3.15 3.15 3.15 6.0 4.2 4.2 4.2 v il low level input voltage 2.0 0.5 0.5 0.5 v 4.5 1.35 1.35 1.35 6.0 1.8 1.8 1.8 v oh high level output voltage 2.0 i o =-20 m a 1.9 2.0 1.9 1.9 v 4.5 i o =-20 m a 4.4 4.5 4.4 4.4 6.0 i o =-20 m a 5.9 6.0 5.9 5.9 4.5 i o =-6.0 ma 4.18 4.31 4.13 4.10 6.0 i o =-7.8 ma 5.68 5.8 5.63 5.6 v ol low level output voltage 2.0 i o =20 m a 0.0 0.1 0.1 0.1 v 4.5 i o =20 m a 0.0 0.1 0.1 0.1 6.0 i o =20 m a 0.0 0.1 0.1 0.1 4.5 i o =6.0 ma 0.17 0.26 0.37 0.37 6.0 i o =7.8 ma 0.18 0.26 0.37 0.37 i i input leakage current 6.0 v i =v cc or gnd 0.1 1 1 m a i oz high impedance output leakage current 6.0 v i =v ih or v il v o =v cc or gnd 0.5 5 10 m a i cc quiescent supply current 6.0 v i =v cc or gnd 44080 m a
m74hc646 6/13 ac electrical characteristics (c l = 50 pf, input t r =t f = 6ns) symbol parameter test condition value unit v cc (v) c l (pf) t a =25 c -40 to 85 c -55 to 125 c min. typ. max. min. max. min. max. t tlh t thl output transition time 2.0 50 25 60 75 80 ns 4.5 7121520 6.0 6101315 t plh t phl propagation delay time (bus - bus) 2.0 50 74 150 190 195 ns 4.5 21 30 38 42 6.0 18 26 32 35 2.0 150 91 190 240 245 ns 4.5 26 38 48 52 6.0 22 32 41 48 t plh t phl propagation delay time (clock - bus) 2.0 50 98 210 265 275 ns 4.5 28 42 53 60 6.0 24 36 45 50 2.0 150 116 250 315 325 ns 4.5 33 50 63 75 6.0 28 43 54 60 t plh t phl propagation delay time (select - bus) 2.0 50 81 170 215 225 ns 4.5 23 34 43 56 6.0 20 29 37 45 2.0 150 98 210 265 275 ns 4.5 28 42 53 60 6.0 24 36 45 50 t pzl t pzh high impedance output enable time (g, dir) 2.0 50 r l =1k w 84 175 220 225 ns 4.5 24 35 44 50 6.0 20 30 37 45 2.0 150 r l =1k w 102 215 270 280 ns 4.5 29 43 54 60 6.0 25 37 46 55 t plz t phz high impedance output disable time (g, dir) 2.0 50 r l =1k w 60 175 220 230 ns 4.5 23 35 44 50 6.0 20 30 37 45 f max maximum clock frequency 2.0 50 6 19 4.8 4.0 mhz 4.5 30 67 24 20 6.0 35 79 28 25 t w(h) t w(l) minimum pulse width 2.0 50 30 75 95 100 ns 4.5 7151922 6.0 6131618 t s minimum set-up time 2.0 50 16 50 65 70 ns 4.5 4101315 6.0 3 9 11 13 t h minimum hold time 2.0 50 555 ns 4.5 5 5 5 6.0 5 5 5
m74hc646 7/13 capacitive characteristics 1) c pd is defined as the value of the ic's internal equivalent capacitance which is calculated from the operating current consumption without load. (refer to test circuit). average operating current can be obtained by the following equation. i cc(opr) =c pd xv cc xf in +i cc /8 (per bit) test circuit c l = 50pf/150pf or equivalent (includes jig and probe capacitance) r 1 =1k w or equivalent r t =z out of pulse generator (typically 50 w ) symbol parameter test condition value unit v cc (v) t a =25 c -40 to 85 c -55 to 125 c min. typ. max. min. max. min. max. c in input capacitance 5101010pf c pd power dissipation capacitance (note 1) 39 pf test switch t plh ,t phl open t pzl ,t plz v cc t pzh ,t phz gnd
m74hc646 8/13 waveform 1 : propagation delay time (f=1mhz; 50% duty cycle) waveform 2 : propagation delay time, minimum pulse width (f=1mhz; 50% duty cycle)
m74hc646 9/13 waveform 3 : minimum pulse width, setup and hold time (f=1mhz; 50% duty cycle) waveform 4 : output enable and disable time (f=1mhz; 50% duty cycle)
m74hc646 10/13 dim. mm. inch min. typ max. min. typ. max. a1 0.63 0.025 b 0.45 0.018 b1 0.23 0.31 0.009 0.012 b2 1.27 0.500 d 32.2 1.268 e 15.2 16.68 0.598 0.657 e 2.54 0.100 e3 27.94 1.100 f 14.1 0.555 i 4.445 0.175 l 3.3 0.130 plastic dip-24 (0.25) mechanical data p043a
m74hc646 11/13 dim. mm. inch min. typ max. min. typ. max. a 2.65 0.104 a1 0.1 0.2 0.004 0.008 a2 2.45 0.096 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.012 c 0.5 0.020 c1 45 (typ.) d 15.20 15.60 0.598 0.614 e 10.00 10.65 0.393 0.419 e 1.27 0.050 e3 13.97 0.550 f 7.40 7.60 0.291 0.300 l 0.50 1.27 0.020 0.050 s8 (max.) so-24 mechanical data po13t f c l e a1 b1 a e d e3 b 24 13 112 c1 s a2
m74hc646 12/13 dim. mm. inch min. typ max. min. typ. max. a 1.1 0.043 a1 0.05 0.15 0.002 0.006 a2 0.9 0.035 b 0.19 0.30 0.0075 0.0118 c 0.09 0.20 0.0035 0.0079 d 7.7 7.9 0.303 0.311 e 6.25 6.5 0.246 0.256 e1 4.3 4.5 0.169 0.177 e 0.65 bsc 0.0256 bsc k0 8 0 8 l 0.50 0.70 0.020 0.028 tssop24 mechanical data c e b a2 a e1 d 1 pin 1 identification a1 l k e 7047476a
m74hc646 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringe ment of patents or other righ ts of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this pub lication are subject to change without notice. thi s pub lication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authori zed for use as critical components in life suppo rt devices or systems without express written approval of stmicroelectronics. ? the st logo is a registered trademark of stmicroelectronics ? 2001 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco singapore - spain - sweden - swit zerland - united kingdom ? http://w ww.st.com 13/13

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